1. Field of the Invention
The present invention relates in general to a video digital/analog signal converter, and in particular to a video digital/analog signal converter having a structure whereby the analog elements of the video D/A converter are separated from the digital elements of the video D/A converter and of arranging current cells of each of channels to one well, thus preventing data crosstalk between neighboring channels, and in addition by arranging the current channels to be disposed in four directions thus preventing errors due to process variations occurring during manufacturing processes whereby a compact chip will be achieved by a correction arrangement of the current cells.
2. Description of the Conventional Art
Conventionally, a video digital/analog converter as shown in FIG. 1, includes a clock generating circuit 10 for generating R, G, and B clocks in order to control digital data of Red, and Green Blue channels; a mid-decoder 20 for decoding digital data synchronized to a clock signal of the clock generating circuit and located at the fight side of the clock generating circuit 10; a data bus 30 for transferring decoded digital data located at the upper side of the clock generating circuit 10 and the mid-decoder 20; an upper decoder 40 for decoding digital data synchronized to a clock signal of the clock generating circuit 10 and inputted from the data bus 30; a data bus 50 for transferring digital data decoded at the upper decoder 40; a current cell matrix 60 for generating current in response to digital data inputted through the data buses 30 and 50 is located in their order; and a bias circuit 70 for applying bias voltage to the current cell matrix 60.
The current cell matrix 60 consists of a plurality of packs each of which consists of channels of each of R, G, and B.
Referring to FIG. 2, one cell unit consists of current cells of each of R (cell 1), G (cell 2), B (cell 3), which are arrayed on a substrate, as shown therein. A stopper for preventing crosstalk is disposed between channels and the resistance which exists between the channels is indicated as `r.`
Referring to FIG. 3, there is shown a conventional current cell circuit. As shown therein, digital data D and a bias voltage vb1 are respectively applied to gates of nMOS transistors M1 and M2 of a differential amplifier. In addition, the source regions of nMOS transistors M1 and M2 are connected to each other and connected to a drain of a nMOS transistor M3. A bias voltage vb2 is applied to a gate of the nMOS transistor M3.
The operation of the conventional video digital/analog converter will now be described.
If digital data controlled by R, G, and B clocks of a clock generating circuit 10 are inputted into the mid-, upper, and lower decoders 20, 40 and 80, the mid-, upper, and lower decoders 20, 40 and 80 decode the inputted digital data and output the decoded data to the current cell matrix 60 through the data buses 30 and 50. Thereafter, the current cell matrix 60 generates current in proportion to a difference between the digital data inputted from the data buses 30 and 50 and a bias voltage supplied from the bias circuit 70. That is, as shown in FIG. 3, if the value of the digital data D applied to the gate of the nMOS transistor M1 is larger than a bias voltage vb1 applied to a gate of the nMOS transistor M2, and if the bias voltage vb2 applied to a gate of the nMOS transistor M3 is larger than a threshold voltage of the nMOS transistor M3, the differentially amplified output current I.sub.o is applied to the drain of the nMOS transistor M3 through the nMOS transistor M1. However, under the aforementioned conditions, if the bias voltage vb1 applied to the gate of the nMOS transistor M2 is larger than digital data D applied to the gate of the nMOS transistor M1, the current Io is applied to the drain of the nMOS transistor M3 through the nMOS transistor M2. Here, the output current I.sub.o and I.sub.o means that the levels thereof are contrary from each other. In addition, the mid-, upper and lower decoders 20, 40 and 80, if assuming the digital data inputted is 8 bits long, process 8 data bits by separating them into three bits and two bits.
A cell matrix 60 of each channel is arranged as shown in FIG. 4. However, since each of the current cells of the conventional current cell matrix 60 is arranged in the same direction, the process variations occurring during mass production appear at every cell in the X- and Y-directions. Accordingly, an integral Non-Linerarity Error affecting the relation between the outputted analog signal against the inputted digital signal might be heat-damaged in the X- and Y-directions thereof. In addition, since the clock generating circuit 10, the mid-, upper and lower decoders 20, 40 and 80, the current cell matrix 60 and the bias circuit 70 are arrayed in one well, the crosstalk in which undesirable digital noise is transferred into the other channels through the interchannel resistance increases and thus the chip size must be increased to avoid this problem.